Over the last several years, significant advances have occurred in increasing the circuit density in integrated circuit chip technology. The ability to provide significantly increased numbers of devices and circuits on an integrated circuit chip has, in turn, created an increased desire to incorporate or integrate additional system functions onto a single integrated circuit chip. In particular, an increasing need exists for joining both memory circuits and logic circuits together on the same integrated circuit chip.
In fabricating dynamic random access memory (DRAM) circuits, the emphasis has been on circuit density along with reduced cost. On the other hand, when fabricating logic circuits, the emphasis is on creating circuits that operate faster. Accordingly, this desire for dual work function creates additional problems with respect to the complexity and relative cost of the fabricating process. For instance, memory circuits achieve increased density requirements by employing self-aligned contacts (borderless bit line contacts), which are easily implemented in a process having a single type, e.g. typically N+ type, gate work function. A buried-channel type PMOSFET is used in creating DRAMs since such permits a single work function gate conductor, N+, to be used throughout the fabrication process. This results in significant cost savings in fabricating DRAMs, but at the expense of creating an inferior performing PMOSFET. On the other hand, logic circuits require both P+ and N+ gated MOSFETs in order to achieve the necessary switching speeds. P+ and N+ gate conductor devices are highly desirable for merged logic and DRAM (MLD) products.
A typical method for obtaining memory arrays having high density along with borderless bit line contacts (borderless to adjacent gate conductor) involves using a gate cap such as a silicon nitride on top of the gate conductor (e.g. polysilicon or composite polysilicon/silicide) for providing protection against bit line to gate conductor shorts when the contact opening is created. For instance, see FIG. 1 wherein numeral 1 is the silicon substrate, 2 represents the gate insulator, 3 the polysilicon gate, 4 the silicon nitride cap, 5 the side wall insulation such as silicon dioxide or silicon nitride and 6 the contact opening.
Even with misalignment as illustrated by the dashed lines in FIG. 1, the gate is protected by a combination of the nitride gate cap and the side wall spacers.
On the other hand, as illustrated in FIG. 2, the logic fabricating process employs gate structures that do not include a cap so that the particular desired gate, P+ or N+, can be created by ion-implanting the necessary dopant from above the gate. The presence of a nitride cap would block off the ion implantation and frustrate or prevent the necessary doping requirement. This is contrary to the fabricating requirements for achieving memory device density which necessitate the presence of a cap on the gate.